The course aims at providing a comprehensive coverage of techniques for designing efficient VLSI architectures for DSP. Towards this, architectural optimization both at block level as well as at logic level will be considered. The key issues that will be taken up are as follows:
- Graphical Representation of DSP Algorithms
- Retiming for Throughput Maximization
- Pipelined and Parallel Filter Structures
- Bit Serial Digital Filters
- Distributed Arithmetic and Multiplierless Realization of Digital Filters
- Redundant Arithmetic
- DSP Architectures: Datapath and Control
- Speed Power Area Accuracy Tradeoff
- Synchronous vs. Asynch. Designs
- Memory Bandwidth Management
- DSP for Embedded Applications
The course also intends to have a few lab sessions in order to demonstrate digital design flow on Field Programmable Gate Array (FPGA), where the following modules may be covered.
1. Behavioural and structural description for design representation and design entry.
2. Validation through functional simulation.
3. Partitioning, Placement and Routing.
4. Post routing simulation for performance analysis.
5. FPGA specific structural optimization with respect to speed and area.
6. Configuration bitstream generation for actual implementation on FPGA.
The course may be viewed as a consolidated form of a semester long, graduate course on VLSI DSP system/architecture design. Participants from academia may thus find the course to be useful to develop similar courses at their respective institutions. Alternatively, the course may also be used as a reference by industrial professionals interested in VLSI design of signal processing and communication systems. The course assumes minimal prerequisites. An undergraduate level knowledge of digital circuit design and elementary DSP operations is sufficient for one to be able to attend the course.
About the Speakers
Prof. Mrityunjoy Chakraborty (coordinator) obtained Bachelor of Engg. (1983), M.Tech. (1985) and Ph.D. (1994) from Jadavpur University, IIT Kanpur and IIT, Delhi respectively. He joined IIT, Kharagpur as a lecturer in 1994, where he presently holds the position of a full professor. Prof. Chakraborty has held many invited, visiting positions in reputed universities abroad. He has been an associate editor of the IEEE Transactions on Circuits and Systems, Part I (2004-2007,2010-2012) and part II (2008-2009), a guest editor of the EURASIP JASP and a TPC member for many important IEEE conferences. The teaching and research interests of Prof. Chakraborty are in digital and adaptive signal processing, VLSI signal processing and DSP for wireless communications, in which he has guided several Ph.D. students and published extensively. Prof. Chakraborty is a fellow of the INAE
Prof. Anindya Sundar Dhar obtained Bachelor of Engg. in Electronics and Telecomm.Engg. from Bengal Engg. College (1987), followed by M.Tech. (1989) and Ph.D. (1994) from IIT Kharagpur. He is presently a professor in the Dept. of Electronics and Electrical Communication Engg., with teaching and research interests in VLSI architecture design for real time signal processing and communication. Prof. Dhar is a key person in the various VLSI related activities in the institute and has been offering many challenging courses in this area over years, apart from carrying out guided, independent and sponsored research in the above areas.